Cypress Semiconductor /psoc63 /LCD0 /CONTROL

Low speed (LS) generator enable 1: enable 0: disable

High speed (HS) generator enable 1: enable 0: disable

HS/LS Mode selection

0 (LS): Select Low Speed (32kHz) Generator (Works in Active, Sleep and DeepSleep power modes).

1 (HS): Select High Speed (system clock) Generator (Works in Active and Sleep power modes only).

LCD driving waveform type configuration.

0 (TYPE_A): Type A - Each frame addresses each COM pin only once with a balanced (DC=0) waveform.

1 (TYPE_B): Type B - Each frame addresses each COM pin twice in sequence with a positive and negative waveform that together are balanced (DC=0).

Driving mode configuration

0 (PWM): PWM Mode

1 (CORRELATION): Digital Correlation Mode

PWM bias selection

0 (HALF): 1/2 Bias

1 (THIRD): 1/3 Bias

2 (FOURTH): 1/4 Bias (not supported by LS generator)

3 (FIFTH): 1/5 Bias (not supported by LS generator)

The number of COM connections minus 2. So: 0: 2 COM’s 1: 3 COM’s … 13: 15 COM’s 14: 16 COM’s 15: undefined

LS enable status bit. This bit is a copy of LS_EN that is synchronized to the low speed clock domain and back to the system clock domain. Firmware can use this bit to observe whether LS_EN has taken effect in the low speed clock domain. Firmware should never change the configuration for the LS generator without ensuring this bit is 0. The following procedure should be followed to disable the LS generator:

1. If LS_EN=0 we are done. Exit the procedure.
2. Check that LS_EN_STAT=1. If not, wait until it is. This will catch the case of a recent enable (LS_EN=1) that has not taken effect yet.
3. Set LS_EN=0.
4. Wait until LS_EN_STAT=0.